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Synopsys Verification IP (VIP) for MIPI D-Phy provides a comprehensive set of protocol, methodology, and verification features, enabling users to achieve accelerated verification closure of MIPI D-Phy.
VIP is based on next generation architecture and implemented in native SystemVerilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage.
Highlights
- Native SystemVerilog/UVM and Verilog
- Source code test suite (optional)
- Runs natively on all major simulators
- Built-in Protocol checks
- Verification plan and coverage
- Verdi? protocol analyzer
- Error injection and exceptions
Key Features
- Specifications: CSI-2 4.0 (CSE), CSI2 3.0, CSI-2 up to 2.1 compliant with DPHY 3.0 up to 2.5, DSI-2 v2.0, DSI-2 v1.1 compliant with D-PHY 3.0 up to 2.5
- D-PHY Serial and Parallel (PPI) Interface
- One to N PHY data lanes and one clock lane.
- High Speed mode for SERIAL and Parallel Interface
- LPDT mode support for SERIAL and Parallel Interface
- ULPS mode support for SERIAL and Parallel Interface
- TRIGGER mode support for SERIAL and Parallel Interface
- Bus Turn Around (BTA)
- D-PHY Serial/PPI level Error Injection
- Controllability of all D-PHY Global operational timing parameters
- Run-Time reconfiguration of Dynamic Parameters
- Support for Alternate Calibration, Preamble, HS-Idle and Sync Patterns
D-PHY VIP Architecture